Implementation of high-speed fixed-point dividers on FPGA

Authors

  • Nikolai Sorokin Pacific National University, Tikhookeanskaya str., 136 , Khabarovsk, Russia

Keywords:

modular design, programmable logic, FPGA, high.precision computations, fixed-point division

Abstract

Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, the speed of the 32-bit designed module is almost 245 MHz vs. 193 MHz from Xilinx divider. Moreover, high-speed parameterized modules are designed to provide arbitrary precision of the fixed-point division, for example, with 64-bit or 128-bit operands and large fixedpoint result.

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References

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Published

2006-04-03

How to Cite

Sorokin, N. (2006). Implementation of high-speed fixed-point dividers on FPGA. Journal of Computer Science and Technology, 6(01), p. 8–11. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/824

Issue

Section

Original Articles