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Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, the speed of the 32-bit designed module is almost 245 MHz vs. 193 MHz from Xilinx divider. Moreover, high-speed parameterized modules are designed to provide arbitrary precision of the fixed-point division, for example, with 64-bit or 128-bit operands and large fixedpoint result.
Articles accepted for publication will be licensed under the Creative Commons BY-NC-SA. Authors must sign a non-exclusive distribution agreement after article acceptance.
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Mean Time to Acceptance Response: 114 days
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ISSN
1666-6038 (Online)
1666-6046 (Print)