A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture


  • Yung-Yuan Chen Department of Computer Science and Information Engineering, Chung-Hua University, Hsin-Chu, Taiwan, R.O.C.


Fault diagnosis, Errors in testing, Reconfigurable arrays, Switching network, Test quality


In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.


Download data is not yet available.


[1] H. Singh et al., “MorphoSys: An Integrated Reconfigurable System for Data-Parallel andComputation-Intensive Applications,” IEEE Trans. On Computers, vol. 49, no. 5, pp. 465-481, May 2000.
[2] K. Bondalapati and V. K. Prasanna, “Reconfigurable Computing Systems,” Proceedings of the IEEE, vol. 90, no. 7, pp120 1-1217, July 2002.
[3] R. Negrini, M. G. Sami and R. Stefanelli. Fault-Tolerance through Reconfiguration of VLSIand WSI Arrays. The MIT Press, 1989.
[4] L. E. LaForge, “Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types,” IEEE Trans. on Computers, vol. 48, no. 4, pp. 398-416, Apr. 1999.
[5] M. Fukushi and S. Horiguchi, “A Self-Reconfigurable Hardware Architecture forMesh Arrays Using Single/Double Vertical Track Switches,”IEEE Trans. on Instrumentation and Measurement, vol. 53, no. 2, pp. 357-367, April 2004.
[6] Y. H. Su, M Cutler and M. Wang, “Self-Diagnosis of Failures in VLSI Tree Array Processors,” IEEE Trans. On Computers, vol. 40, no. 11, pp. 1252-1257, Nov. 1991.
[7] D. M. Blough and A. Pelc, “Diagnosis and Repair in Multiprocessor Systems,” IEEE Trans. on Computers, vol. 42, no. 2, pp. 205-217, Feb. 1993.
[8] J. Salinas and F. Lombardi, “Diagnosis ofReconfigurable Two-Dimensional arrays Using a Scan Approach,” 6th annual IEEE Int’l Conf. on Wafer Scale Integration, pp. 179-187, 1994.
[9] K. C. Wang and J. W. Lin, “Integrated Diagnosis and Reconfiguration Process for Defect Tolerant WSI Processor arrays,” 6th annual IEEE Int’l Conf. on Wafer Scale Integration, pp. 198-207, 1994.
[10] S. Goldberg and S. J. Upadhyaya, “Utilizing Spares in Multichip Modules for the Dual function of FaultCoverage and Fault Diagnosis,” IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 234-242, 1995.
[11] F. J. Meyer, F. Lombardi and J. Zhao, “Good Processor Identification in Two-Dimensional Grids,” IEEE Int’l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 348-356, 1999.
[12] S. Goldberg, S. J. Upadhyaya and W. K. Fuchs,“Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares,” IEEE Trans. on Reliability, vol. 53, no. 4, pp. 445-451, Dec. 2004.
[13] S. Y. Kuo, K. C. Wang, “Fault Diagnosis in Reconfigurable VLSI and WSI Processor Arrays,” Journal of VLSI Signal Processing 2, pp. 173-187, 1990.
[14] A. Jain, B. Mandava, J. Rajski and N. C. Rumin, “A Fault-Tolerant Array Processor Designed for Testability and Self-Reconfiguration,” IEEE Journal of Solid-State Circuits, vol. 26, no. 5, May 1991.
[15] S. Rangarajan, D. Fussell, M. Malek, “Efficient Fault Diagnosis of Switches in Wafer Arrays,” 4th annual IEEE Int’l Conf. on Wafer Scale Integration, pp. 341-351, 1992.
[16] Y. Y. Chen, C. H. Cheng and Y. C. Chou, “An Effective Reconfiguration Process forFault-Tolerant VLSI/WSI Array Processors,” EDCC-1, pp. 421-438, Oct. 1994.
[17] R. H. Williams, C. F. Hawkins, “Errors in Testing,” Int’l Test Conf., pp. 1018-1027, 1990.
[18] K.J. Lee, M.A. Breuer, “A Universal Test Sequence for CMOS Scan Registers,” IEEE Custom Integrated Circuit Conf., pp. 28.5.1-28.5.4, 1990.




How to Cite

Chen, Y.-Y. (2006). A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture. Journal of Computer Science and Technology, 6(01), p. 12–21. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/822



Original Articles