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Utilizing block size variability to enhance instruction fetch rate
Keywords:
Basic blocks, Instruction cache, Trace cache, Block cacheAbstract
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks.
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References
[1] J. Hennessy, and D. Patterson, “Computer Architecture: A Quantitative Approach,” 3rd ed., Morgan . Kaufman Publishers, Inc, CA, 2003.
[2] E. Hao, P.Y. Chang, M. Evers, and Y. Patt, “Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,” Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, pages 191 – 200, 1996.
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[8] S. Patel, D. Friendly, and Y. Patt, “Evaluation of Design Option for the Trace Cache Fetch Mechanism,” IEEE Transactions on Computers, Volume 48, Issue 2, pages 193 –204, Feb 1999.
[9] S. Patel, M. Evers, and Y. Patt, “Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing,” Proceedings of 25th Annual International Symposium on Computer Architecture, pages 262 –271, 1998.
[10] D. Howard, and M. H. Lipasti, “The Effect of Program Optimization on Trace Cache Efficiency,” Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pages 256 – 261, 1999.
[11] B. Black, B. Rychlick, and J. Shen, “The Block-Based Trace Cache,” Proceedings of the 26th International Symposium on Computer Architecture, pages 196 – 207, 1999.
[12] K. Kavi, A. R. Hurson, P. Patadia, E. Abraham, and P. Shanmugam, “Design of cache memories for multi-threaded dataflow architecture,” Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.
[13] P. Kakulavarapu, et al, “A comparative performance study of a fine-grain multi-threading model on distributed memory machines,” Proceeding of the IEEE International Conference on Performance, Computing, and Communications Conference, Feb. 2000.
[14] L. Alkalaj, “Performance of multi-threaded execution in a shared-memory multiprocessor,” Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, Dec. 1991.
[15] D. Lioupis, and S. Milios, “Exploring cache performance in multithreaded processors,” Microprocessors and Microsystems, Volume 20, Issue 10, July 1997.
[16] D. Burger, and T. Austin, “The SimpleScalar Tool Set, Version 2.0,” University of Wisconsin-Madison Computer Sciences Department Technical Report #1242, June 1997.
[17] http://www.simplescalar.com/
[18] http://www.specbench.org/cpu2000/
[19] J. Gummaraju, and M. Franklin, “Branch prediction in multi-threaded processors,” Proceedings of International Conference on Parallel Architectures and Compilation Techniques, Oct. 2000.
[20] A. Hossain, “Trace Cache in Simultaneous Multi-threading,” PhD dissertation, Dept. of Computer Engineering, Syracuse University, 2002.
[2] E. Hao, P.Y. Chang, M. Evers, and Y. Patt, “Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,” Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, pages 191 – 200, 1996.
[3] S. Dutta, and M. Franklin, “Control Flow Prediction with Tree-Like Sub-Graphs for Superscalar Processors,” Proceedings of the 28th Annual International Symposium on Microarchitecture, pages 258 – 263, 1995.
[4] S. Dutta, and M. Franklin, “Control Flow Prediction Schemes for Wide-Issue Superscalar Processors,” IEEE Transactions on Parallel and Distributed Systems, Volume 10, Issue 4, pages 346 – 359, April 1999.
[5] E. Rotenberg, S. Bennett, and J. E. Smith, “A Trace Cache Microarchitecture and Evaluation,” IEEE Transactions on Computers, Volume 48, Issue 2, pages 111 – 120, February 1999.
[6] D.L. Howard, and M.H. Lipasti, “The Effect of Program Optimization on Trace Cache Efficiency,” Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pages 256 – 261, 1999.
[7] Q. Jacobson, and J. Smith, “Trace Preconstruction,” Proceedings of the 27th International Symposium on Computer Architecture, pages 37 – 46, 2000.
[8] S. Patel, D. Friendly, and Y. Patt, “Evaluation of Design Option for the Trace Cache Fetch Mechanism,” IEEE Transactions on Computers, Volume 48, Issue 2, pages 193 –204, Feb 1999.
[9] S. Patel, M. Evers, and Y. Patt, “Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing,” Proceedings of 25th Annual International Symposium on Computer Architecture, pages 262 –271, 1998.
[10] D. Howard, and M. H. Lipasti, “The Effect of Program Optimization on Trace Cache Efficiency,” Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pages 256 – 261, 1999.
[11] B. Black, B. Rychlick, and J. Shen, “The Block-Based Trace Cache,” Proceedings of the 26th International Symposium on Computer Architecture, pages 196 – 207, 1999.
[12] K. Kavi, A. R. Hurson, P. Patadia, E. Abraham, and P. Shanmugam, “Design of cache memories for multi-threaded dataflow architecture,” Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.
[13] P. Kakulavarapu, et al, “A comparative performance study of a fine-grain multi-threading model on distributed memory machines,” Proceeding of the IEEE International Conference on Performance, Computing, and Communications Conference, Feb. 2000.
[14] L. Alkalaj, “Performance of multi-threaded execution in a shared-memory multiprocessor,” Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, Dec. 1991.
[15] D. Lioupis, and S. Milios, “Exploring cache performance in multithreaded processors,” Microprocessors and Microsystems, Volume 20, Issue 10, July 1997.
[16] D. Burger, and T. Austin, “The SimpleScalar Tool Set, Version 2.0,” University of Wisconsin-Madison Computer Sciences Department Technical Report #1242, June 1997.
[17] http://www.simplescalar.com/
[18] http://www.specbench.org/cpu2000/
[19] J. Gummaraju, and M. Franklin, “Branch prediction in multi-threaded processors,” Proceedings of International Conference on Parallel Architectures and Compilation Techniques, Oct. 2000.
[20] A. Hossain, “Trace Cache in Simultaneous Multi-threading,” PhD dissertation, Dept. of Computer Engineering, Syracuse University, 2002.
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Published
2007-04-02
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[1]
“Utilizing block size variability to enhance instruction fetch rate”, JCS&T, vol. 7, no. 02, pp. p. 155–161, Apr. 2007, Accessed: Apr. 14, 2026. [Online]. Available: https://journal.info.unlp.edu.ar/JCST/article/view/786
