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Power-efficient memory bus encoding using stride-based stream reconstruction
Keywords:
Bus Encoding, Low Power, Interconnection, SOCAbstract
With the rapid increase in the complexity of chips and the popularity of portable devices, the performance demand is not any more the only important constraint in the embedded system. In stead, energy consumption has become one of the main design issues for contemporary embedded systems, especially for I/O interface due to the high capacitance of bus transition. In this paper, we propose a bus encoding scheme, which may reduce transitions by reconstructing active address streams with variable cached strides. The key idea is to obtain the variable strides for dierent sets of active addressing streams such that the decoder reconstructs these interlaced streams with these strides. Instead of sending the full address, the encoder may only send partial ad- dress or stride by using either one-hot or binary-inversion encoding. To exploit the locality and dynamically adjust the value of stride of active address streams, we partially compare the previous addresses of existing streams with the current address. Hence, the data transmitted on the bus can be minimally encoded. Experiments with several MediaBench benchmarks show that the scheme can achieve an average of 60% reduction in bus switching activity.
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References
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[11] M.Mamidipaka, D. Hirschberg, and N. Dutt. Low power address encoding using self-organizing lists. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 188-193, 2001.
[12] M. Mamidipaka, D. Hirschberg, and N.Dutt. Adaptive low-power address encoding techniques using self-organizing lists. IEEE Transaction on Very Large Scale Integration Systems, 11(5):827-834, 2003.
[13] E. Musoll, T. Lang, and J. Cortadella. Exploiting the locality of memory references to reduce the address bus energy. In Proceedings of International Symposium on Low power Electronics and Design, pages 202-207, 1997.
[14] E. Musoll, T. Lang, and J. Cortadella. Working-zone encoding for reduce energy in microprocessor address buses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):568-572, 1998.
[15] M. Powell, S.-H. Yang, B. Falsa , K. Roy, and T. N. Vijaykumar. Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 90-95, July 2000.
[16] S. Ramprasad, N.R. Shanbhag, and I.N. Hajj. A coding framework for low-power address and data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(2):212-221, 1999.
[17] T.Arslan S. Osborne, A.T. Erdogan and D. Robinson. Bus encoding architecture for low-power implementation of an AMBA-based SoC platform. IEEE Proceedings-Computers and Digital Techniques, 149(4):152-156, 2002.
[18] M. R. Stan and W. P. Burleson. Bus-Invert coding for low-power I/O. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1):49-58, 1995.
[2] Y. Aghaghiri, F. Fallah, and M. Pedram. BEAM: bus encoding based on instruction-sef-aware memories. In Proceedings of the Asia and South Pacic Design Automation Conference (ASP-DAC), pages 3-8, 2003.
[3] Y. Aghaghiri, F. Fallah, and M. Pedram. Transition reduction in memory buses using sector-based encoding techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(8):1164-1174, 2004.
[4] Doug Burger and Todd M. Austin. The simplescalar tool set, version 2.0. http://www.simplescalar.com, June 1997.
[5] P. J. Denning. The working set model for program behavior. Communications of the ACM, 11(5):323-333, 1968.
[6] D. Eppstein and T. D. Givargis. Reference caching using unit distance redundant codes for activity reduction on address buses. In Proceedings of the International Workshop on Embedded System Codesign (ESCODES'02), pages 43-48, 2002.
[7] K. Flautner, N.S. Kim, S. Martin, D.Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leak age power. In Proceedings of the International Symposium on Computer Architecture, pages 219-230,2002.
[8] W. Fornaciari, M. Polentarutti, D. Sciuto, and C. Silvano. Power optimization of system-level address buses based on software pro ling. In Proceedings of the Eighth International Workshop on Hardware/Software Codesign, pages 29{33,2000.
[9] E. Macii D.Sciuto L. Benini, G. De Micheli and C. Silvano. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems. In Proceedings of the 13th Annual Intl. Symp. on Computer Architecture, 1986.
[10] T.Lv, J. Henkel, H. Lekatsas, and W. Wolf. A dictionary-based en/decoding scheme for low-power data buses. IEEE Transactions on Very Large Scale Integration Systems, 11(5):943-951, 2003.
[11] M.Mamidipaka, D. Hirschberg, and N. Dutt. Low power address encoding using self-organizing lists. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 188-193, 2001.
[12] M. Mamidipaka, D. Hirschberg, and N.Dutt. Adaptive low-power address encoding techniques using self-organizing lists. IEEE Transaction on Very Large Scale Integration Systems, 11(5):827-834, 2003.
[13] E. Musoll, T. Lang, and J. Cortadella. Exploiting the locality of memory references to reduce the address bus energy. In Proceedings of International Symposium on Low power Electronics and Design, pages 202-207, 1997.
[14] E. Musoll, T. Lang, and J. Cortadella. Working-zone encoding for reduce energy in microprocessor address buses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):568-572, 1998.
[15] M. Powell, S.-H. Yang, B. Falsa , K. Roy, and T. N. Vijaykumar. Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 90-95, July 2000.
[16] S. Ramprasad, N.R. Shanbhag, and I.N. Hajj. A coding framework for low-power address and data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(2):212-221, 1999.
[17] T.Arslan S. Osborne, A.T. Erdogan and D. Robinson. Bus encoding architecture for low-power implementation of an AMBA-based SoC platform. IEEE Proceedings-Computers and Digital Techniques, 149(4):152-156, 2002.
[18] M. R. Stan and W. P. Burleson. Bus-Invert coding for low-power I/O. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1):49-58, 1995.
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Published
2007-04-02
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[1]
“Power-efficient memory bus encoding using stride-based stream reconstruction”, JCS&T, vol. 7, no. 02, pp. p. 148–154, Apr. 2007, Accessed: Apr. 15, 2026. [Online]. Available: https://journal.info.unlp.edu.ar/JCST/article/view/785
