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A low cost advance encryption standard (AES) co-processor implementation
Keywords:
FPGA Design, VLSI Design, AES, Cryptographic Architectures, Specialized ArchitecturesAbstract
The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
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References
[1] National Institute of Standards and Technology (US), Advanced Encryption Standard, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.
[2] S.-M. Yoo, D. Kotturi, D.W. Pan and J. Blizzard, An AES crypto chip using a high-speed parallel pipelined architecture, Microprocessors and Microsystems 29 (2005) 317-326.
[3] X. Zhang, and K. Parhi, High-speed VLSI architectures for the AES algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2004) 957-967.
[4] C-P. Su, T.-F. Lin, C.-T. Huang and C.-W. Wu, A high throughput low-cost AES processor, IEEE Communications 41 (2003) 86-91.
[5] V. Fischer and M. Drutarovsky, Two methods of Rijndael implementation in reconfigurable hardware, Proc. CHES, Vol. 2162, France, 2001, pp.81-96.
[6] E. Mang, I. Mang and C. Popescu, AES Candidate Algorithm Finalists: FPGA implementation and performance evaluation, Proc. of the IASTED International Conference, 2003, pp. 147-152.
[7] N. Pramstaller, S. Mangard, S. Dominikus and J. Wolkerstorfer, Efficient AES implementations on ASICs and FPGAs, Lecture Notes in Computer Science 3373 (2005) 98-112.
[8] L. Chang-Shu, P. Gen-Peng and W. Xio-Zhuo, Two methods of AES implementation based on CPLD/FPGA, Transactions of Tianjin University 10 (2004) 285-290.
[9] A. J. Elbirt, W. Yip, B. Chetwynd and C. Paar, An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2001) 545-557.
[10] N. Sklavos and O. Koufopavlou, Architectures and VLSI implementations of the AES - Proposal Rijndael, IEEE Transactions on Computers 51 (2002) 1454-1459.
[11] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater and J.-D. Legat, Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications, Proc. of the International Conference on Information Technology: Coding Computing - ITCC, Vol. 2, USA, 2004, pp. 583-587.
[12] M. McLoone and J. McCanny, Rijndael FPGA implementations utilizing look-up tables, Journal of VLSI Signal Processing, 34 (2003) 261-275.
[2] S.-M. Yoo, D. Kotturi, D.W. Pan and J. Blizzard, An AES crypto chip using a high-speed parallel pipelined architecture, Microprocessors and Microsystems 29 (2005) 317-326.
[3] X. Zhang, and K. Parhi, High-speed VLSI architectures for the AES algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2004) 957-967.
[4] C-P. Su, T.-F. Lin, C.-T. Huang and C.-W. Wu, A high throughput low-cost AES processor, IEEE Communications 41 (2003) 86-91.
[5] V. Fischer and M. Drutarovsky, Two methods of Rijndael implementation in reconfigurable hardware, Proc. CHES, Vol. 2162, France, 2001, pp.81-96.
[6] E. Mang, I. Mang and C. Popescu, AES Candidate Algorithm Finalists: FPGA implementation and performance evaluation, Proc. of the IASTED International Conference, 2003, pp. 147-152.
[7] N. Pramstaller, S. Mangard, S. Dominikus and J. Wolkerstorfer, Efficient AES implementations on ASICs and FPGAs, Lecture Notes in Computer Science 3373 (2005) 98-112.
[8] L. Chang-Shu, P. Gen-Peng and W. Xio-Zhuo, Two methods of AES implementation based on CPLD/FPGA, Transactions of Tianjin University 10 (2004) 285-290.
[9] A. J. Elbirt, W. Yip, B. Chetwynd and C. Paar, An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2001) 545-557.
[10] N. Sklavos and O. Koufopavlou, Architectures and VLSI implementations of the AES - Proposal Rijndael, IEEE Transactions on Computers 51 (2002) 1454-1459.
[11] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater and J.-D. Legat, Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications, Proc. of the International Conference on Information Technology: Coding Computing - ITCC, Vol. 2, USA, 2004, pp. 583-587.
[12] M. McLoone and J. McCanny, Rijndael FPGA implementations utilizing look-up tables, Journal of VLSI Signal Processing, 34 (2003) 261-275.
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Published
2008-04-01
How to Cite
Hernandez, O. J., Sodon, T., Adel, M., & Kupp, N. (2008). A low cost advance encryption standard (AES) co-processor implementation. Journal of Computer Science and Technology, 8(01), p. 8–14. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/762
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Original Articles
