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Hardware radial basis function neural network automatic generation
Keywords:
RBF Neural Networks, FPGA, Pattern recognition, ArchitectureAbstract
This paper presents a parallel architecture for a radial basis function (RBF) neural network used for pattern recognition. This architecture allows defining sub-networks which can be activated sequentially. It can be used as a fruitful classification mechanism in many application fields. Several implementations of the network on a Xilinx FPGA Virtex 4-(xc4vsx25) are presented, with speed and area evaluation metrics. Some network improvements have been achieved by segmenting the critical path. The results expressed in terms of speed and area are satisfactory and have been applied to pattern recognition problems.
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References
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[2] J. Moody and C. Darken, “Learning with localized receptive fields,” Proc. Connectionist Models Summer School, San Mateo, CA, 1988.
[3] I. Park and I. W. Sandberg, “Universal approximation using radial basis function networks,” Neural Computat., vol. 3, pp. 246–257, 1991.
[4] StatSoft Inc, “Neural www.statsoftinc.com, 2003.
[5] N. Acosta, M. Tosini, “Custom Architectures for Fuzzy Logic and Neural Networks Controllers”, Journal of Computer Science & Technology, ISBN 1666-6064, pp. 9-20, 2002
[6] Valeriu Beiu, “Digital integrated circuit implementations”, Handbook of Neural Computation release 97/1, Publishing Ltd and Oxford University Press,1997.
[7] Clark S. Lindsey , Bruce Denby , & Thomas Lindblad, “Neural Network Hardware”, http://neuralnets.web.cern.ch/NeuralNets/nnwInHep.html, 1998.
[8] Yihua Liao, “Neural Networks in Hardware: A Survey”, Department of Computer Science, University of California, 2001.
[9] Silicon Recognition, “ZISC: Zero Instruction Set Computer”, Version 4.2, Silicon Recognition, Inc., 2002
[10] Z. Uykan, “Clustering-Based Algorithms for Radial Basis Function and Sigmoid Perceptron Networks,”
Ph.D. dissertation, Control Eng. Lab.,Helsinki Univ. Technol., Helsinki, Finland, 2001.
[11] Cognimem, CogniMem_1K: Neural network chip for high performance pattern recognition, datasheet, Version 1.2.1, www.recognetics.com, 2008.
[12] Xilinx, Inc. Virtex-4 User Guide, UG070 (v2.6). www.xilinx.com, 2008.
[13] Xilinx, Inc. Xilinx Synthesis Technology (XST) User Guide. UG627 (v 11.1.0) www.xilinx.com, 2009.
[14] Xilinx, Inc. ISE www.xilinx.com, 2009. 9.1.03i Documentation.
[15] L. Leiva, “Herramienta para Diseño Automático de Arquitecturas Basadas en Redes Neuronales para Reconocimiento de Patrones Visuales”, Graduation thesis, System Engineering, UNCPBA, 2006.
[16] L. Leiva, M. Vázquez, N. Acosta, G. Sutter, “Herramienta de Generación de Arquitecturas Hardware para Reconocimiento de Patrones en Imágenes”, JCRA 2007: Jornadas de Computación Reconfigurable y Aplicaciones. September 12-14, 2007, Zaragoza, España.
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Published
2011-04-01
How to Cite
Leiva, L., & Acosta, N. (2011). Hardware radial basis function neural network automatic generation. Journal of Computer Science and Technology, 11(01), p. 15–20. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/683
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Original Articles
