High Performance Customizable Architecture for Machine Vision Applications

Authors

  • Lucas Leiva INCA/INTIA, Facultad de Ciencias Exactas, Universidad Nacional del Centro de la Prov. De Bs. As, Tandil, 7000, Argentina
  • Nelson Acosta INCA/INTIA, Facultad de Ciencias Exactas, Universidad Nacional del Centro de la Prov. De Bs. As, Tandil, 7000, Argentina

Keywords:

FPGA, Video Processing, Machine Vision

Abstract

Vision based applications are present anywhere. A special market is industry, allowing to improve product quality and to reduce manufacturing costs. The vision systems applied to industries are known as machine vision systems. These systems must meet time constraints to operate in real time. Generally the production lines are more and more fasters, and the time to process and bring a response is minimal. For this reasons, dedicated architectures are emplaced. In this work a review of several commercial systems is presented, as well a proposed architecture is depicted. The architecture is concern as a customizable platform, avoiding having knowledge in hardware description languages. It is based on massive parallelism to achieve the maximum processing performance. Several optimizations at different levels are applied to increase the final system speedup. Also, time and area metrics are reported, showing that the architecture is well suitable for real time video processing in industrial applications.

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References

[1] Philips, “Programmable Media Processor – TriMedia TM-1300”. Internal Report. Processor datasheet. 2001. Pp: 1-9.
[2] J. Brambor: “Implementation notes of binary dilation and erosion on 64-bit SH5 processor”. Centre de Morphologie Mathematique, Ecole National Superieur des Mines de Paris, France. October 2002. Pp: 1-17.
[3] HP: “Inside the Intel Itanium 2 Processor”. A Hewlett-Packard Technical White Paper. 2002. Pp: 1-44.
[4] Orly Yadid-Pecht, Ralph Etienne-Cumming, CMOS Imagers: From Phototransduction to Image Processing, Springer, 2004
[5] A. Zarandy, Focal-Plane Sensor-Processor Chips, ISBN 9781441980076, Springer, 2011.
[6] A. Rodríguez-Vázquez, R. Domínguez-Castro, F. Jiménez-Garrido, S. Morillas, A. García, C. Utrera, M. Dolores Pardo, J. Listan, R. Romay, “A CMOS Vision System On-Chip with Multi-Core, Cellular Sensory-Processing Front-End”, In Cellular Nanoscale Sensory Wave Computing, C. Baatar, W. Porod, T. Roska, ISBN: 978–1–4419–1010–3, 2009
[7] P.Dudek, D.R.W.Barr, A.Lopich and S.J. Carey, “Demonstration of real-time image processing on the SCAMP-3 vision system”, IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2006, pp.13-13, Istanbul, August 2006
[8] J. Poikonen, M. Laiho, and A. Paasio, MIPA4k: A 64×64 cell mixed-mode image processor array, in IEEE International Symposium on Circuits and Systems Taiwan, 2009, pp. 1927–1930
[9] A.Lopich and P.Dudek, "ASPA: Focal Plane Digital Processor Array with Asynchronous Processing Capabilities", IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp 1592-1596, May 2008
[10] A.Lopich and P.Dudek, "Implementation of an Asynchronous Cellular Logic Network as a Co-Processor for a General-Purpose Massively Parallel Array", European Conference on Circuit Theory and Design, ECCTD 2007, pp.84-87, Seville, Spain, August 2007
[11] P. Földesy, R. Carmona-Galan, A ́ . Zarándy, C. Rekeczky, A. Rodríguez-Vázquez, T. Roska, 3D multi-layer vision architecture for surveillance and reconnaissance applications, ECCTD-2009, Antalya, Turkey
[12] A. W. Azman, A. Bigdeli, Y. M. Mustafah, and B. C. Lovell: “Optimizing resources on an FPGA-based
smart camera architecture”. Digital image computing techniques and applications. 2007. Pp. 600-606.
[13] A. gentile and D. Scott Wills: “Portable video supercomputing”. IEEE Transactions on Computers, Vol 53, Nro 8, August 2004. Pp: 960-973.
[14] Dalsa, "XRI-1200: PC based Digital Image Processor for X-ray Imaging", Datasheet, www.teledynedalsa.com, 2007.
[15] C. Wu, H. Aghajan, and R. Kleihorst: “Mapping vision algorithms on SIMD architecture smart cameras”. ICDSC 07, 2007. Pp: 27-34.
[16] Z. Xiao and B. Zhang, "Parallel image processing based on pipeline", in Proc. Geoinformatics, 2010, pp.1-4.
[17] H. Norell, N. Lawall and M. O’Nils: “Automatica generation of spatial and temporal memory architectures for embedded video processing Systems”. EURASIP Journal on Embedded Systems, Volumen 2007, Article ID 75368. 2007. DOI: 10.1155/2007/75368. Pp: 1-11.
[18] Mahendra G. Samarawickrama: “Performance evaluation of vision algorithms on FPGA”. ISBN: 1-59942-373-1. 2010. Pp: 1-25.
[19] Ahmed Nabil Belbachir: “Smart Cameras”. Springer. ISBN: 978-1-4419-0952-7. DOI: 10.1007/978-1-4419-0953-4. 2009. Pp: 1-394.
[20] N. Kehtarnavaz and M. Gamadia: “Real-Time image and video processing: From research to reality”. Springer. DOI: DOI 10.2200 / S00021 ED1 V01Y 2006 04IVM 005. A publication in the Morgan and Claypool Publishers 2006. Pp: 1-108.
[21] B. Kisacanin, S. Bhattacharyya and S. Chai: “Embedded Computer Vision: Advances in Pattern Recognition”. ISBN 978-1-84800-303-3. DOI 10.1007/978-1-84800-304-0. Springer-Verlag London. 2009. Pp: 1-300.
[22] Alexander Hornberg: “Handbook of Machine Vision”. ISBN-13: 978-3-527-40584-8. Wiley-VCH 2006. Pp: 1-823.
[23] W. E. Snyder and Hairong Qi: “Machine Vision”. ISBN: 978-0-521-83046-1. Cambridge Press. 2007. Pp: 27-34.
[24] E. R. Davies: “Machine Vision. Theory, Algorithms and Practices”. ISBN: 8131201775, Elsevier Press. Oxford University Press. 2003. Pp: 1-938.
[25] Kello Suech: “Understanding and Applying Machine Vision”. ISBN: 0-8247-8929-6. by Marcel Dekker, Inc. 2000. Pp: 1-336.
[26] Najeem Lawal: “Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems”. Mid Sweden University Doctoral Thesis. 2009. ISBN 978-91-86073-26-8.
[27] L. Leiva, N. Acosta, “Detección Rápida de Puntos Salientes en Imágenes”, XV Workshop Iberchip, 25 a
27 de marzo 2009, Buenos Aires, Argentina.
[28] L. Leiva, N. Acosta,"MISD Compiler for Feature Vector Computation in Serial Input Images", ARPN
Journal of Systems and Software. vol. 1, no. 3, pp: 108-116, June 2011.
[29] Silicon Recognition, “ZISC: Zero Instruction Set Computer”, Version 4.2, Silicon Recognition, Inc., 2002
[30] Cognimem, CogniMem_1K: Neural network chip for high performance pattern recognition, datasheet, Version 1.2.1, www.recognetics.com, 2008.
[31] L. Leiva, N. Acosta, "Hardware Radial Basis Function Neural Network Automatic Generation", JCS&T: Journal of Computer Science & Technology. vol. 11, no. 1,pp: 15-20, April 2011.

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Published

2012-04-02

How to Cite

Leiva, L., & Acosta, N. (2012). High Performance Customizable Architecture for Machine Vision Applications. Journal of Computer Science and Technology, 12(01), p. 1–8. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/660

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Section

Invited Articles