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Write management mechanisms for systems with non-volatile memory technologies
Abstract
Since the beginning of computer systems, the memory subsystem has always been one of their essential components. However, the different pace of change between microprocessor and memory has become one of the greatest challenges that current designers have to address in order to develop more powerful computer systems. This problem, called memory gap, is further compounded by the limited scalability and the high energy consumption of conventional memory technologies (DRAM and SRAM), which has leaded to consider new nonvolatile memory (NVM) technologies as potential candidates to replace them. Among NVMs, PCM and STTRAM are currently postulated as the best alternatives. Although PCM and STT-RAM have significant advantages over DRAM and SRAM, they also suffer from some drawbacks that need to be mitigated before they can both be employed as memory technologies for the next computers generation. Notably, the slow and energy-hungry write operations on both technologies, and the limited endurance of PCM cells, which become unchangeable after performing a relatively reduced amount of writes on them, are the main constraints of PCM and STT-RAM technologies. This thesis presents two proposals aimed to efficiently manage the write operations on this kind of memories.
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References
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[2] JL Hennessy and DA Patterson, Computer architecture: a quantitative approach. Morgan K. Pub, 2011.
[3] M. Chaudhuri, “Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches”,
in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, pp. 401–412.
[4] C.J. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. C. Steely, and J. S. Emer, “SHiP: signature-based hit
predictor for high performance caching”, in Int. Symposium on Microarchitecture, MICRO 2011, pp. 430–441.
[5] A. Jaleel, K. B. Theobald, S. C. Steely, and J. S. Emer, “High performance cache replacement using re-
reference interval prediction (RRIP)”, in Int. Symposium on Computer Architecture (ISCA), 2010, pp. 60–71.
[6] R. Rodríguez-Rodríguez, F. Castro, D. Chaver, L. Piñuel, and F. Tirado, “Reducing writes in phase-change
memory environments by using efficient cache replacement policies”, in Design, Automation and Test in Europe (DATE), 2013, pp. 93–96.
[7] R. Rodríguez-Rodríguez, F. Castro, D. Chaver, R. Gonzalez-Alberquilla, L. Piñuel, and F. Tirado, “Write-
aware replacement policies for PCM-based systems”, The Computer Journal, 58 (9), pp. 2000–2025, 2015.
[8] J. Albericio, P. Ibáñez, V. Viñals, and J. M. Llabería, “Exploiting Reuse Locality on Inclusive Shared Last-
level Caches”, ACM Trans. Archit. Code Optim., vol. 9, no. 4, 38:1–38:19, Jan. 2013.
[9] J. Díaz, T. Monreal, V. Viñals, P. Ibáñez, and J. M. Llabería, “Selección de contenidos basada en reuso para caches compartidas en exclusión”, in Proceedings of the XXVI Jornadas de Paralelismo, ser, 2015, pp. 433–442.
[10] J. Ahn, S. Yoo, and K. Choi, “DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture”, in
International Symposium on High Performance Computer Architecture (HPCA), 2014, pp. 25–36.
[11] J.C. Saez, A. Pousa, R. Rodríguez-Rodríguez, F. Castro, M. Prieto-Matías: “PMCTrack: Delivering Performance Monitoring Counter Support to the OS Scheduler”. Comput. J. 60(1): 60-85 (2017).
[12] K. Nguyen, Intel’s Cache Monitoring Technology Software-Visible Interfaces, https://software.intel.com/en-us/blogs/2014/12/11/intels-cache- monitoring- technology-software\- visible-interfaces, 2014.
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Published
2017-04-01
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[1]
“Write management mechanisms for systems with non-volatile memory technologies”, JCS&T, vol. 17, no. 01, pp. p. 85–86, Apr. 2017, Accessed: Jul. 08, 2025. [Online]. Available: https://journal.info.unlp.edu.ar/JCST/article/view/446
