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Communion: a new strategy form memory management in high-performance computer
Abstract
Modern computers present a big gap between peak performance and sustained performance. There are many reasons for this situation, but mainly involving an inefficient usage of computational resources. Nowadays the memory system is the most critical component because of its growing inability to keep up with the processor requests. Technological trends have produced a large and growing gap between CPU speeds and DRAM speeds. Much research has focused this memory system problem, including program optimizing techniques, data locality enhancement, hardware and software prefetching, decoupled architectures, multithreading, speculative loads and execution. These techniques have got a relative success, but they focus only one component in the hardware or software systems. We present here a new strategy for memory management in high-performance computer systems, named COMMUNION. The basic idea behind this strategy is "cooperation". We introduce some interaction possibilities among system programs that are responsible to generate and execute application programs. So, we investigate two specific interactions: between the compiler and the operating system, and among the compiling system components. The experimental results show that it's possible to get improvements of about 10 times in execution time, and about 5 times in memory demand, enhancing the interaction between the compiling system components. In the interaction between compiler and operating system, named Compiler-Aided Page Replacement (CAPR), we achieved a reduction of about 10% in space-time product, with an increase of only 0.5% in the total execution time. All these results show that it s possible to manage main memory with a better efficiency than current systems.
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References
[1] AHO, A.V.; SETHI, R.; ULLMAN, J.D. Compilers - principles, techniques and tools. Addison-Wesley, 1986.
[2] BANERJEE, U. Loop parallelization. Kluwer Academic Publishers, 1994.
[3] COCKCROFT, A. Sun performance and tuning: sparc & solaris. Prentice-Hall, 1995.
[4] EISENBEIS, C. et alii. A strategy for array management in local memory. Rapports de Recherche no 1262. INRIA, France. 1990.
[5] FRANKLIN, M. A. et alii. Anomalies with variable partition paging algorithms. Communications of the ACM, 21:3, p.232-236, 1978.
[6] K. Hwang. Advanced computer architecture: parallelism, scalability, programmability. McGraw-Hill, 1993.
[7] KREMER, U. Automatic data layout for distributed memory machines. Ph.D. Thesis. Computer Science Department, Rice University. 1995.
[8] MALKAWI, M. I. Compiler directed memory management for numerical programs. Ph.D. Thesis. Department of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign. 1986.
[9] MARINO, M. D. Pulsar: um sistema de memória virtual compartilhada e distribuída, baseado em consistência relaxada. Master Thesis, Polytechnic School, University of São Paulo, 1996.
[10] MIDORIKAWA, E. T. Análise da otimização de acessos à memória. In: Proceedings of 6th Brazilian Symposium on Computer Architecture - High Performance Computing, p.37-52, Caxambu, MG, Brazil, August 1994.
[11] MIDORIKAWA, E. T. et alii. Um sistema integrado para otimização automática de paralelismo e localidade de dados. In: Proceedings of 7th Brazilian Symposium on Computer Architecture - High Performance Computing, p.523-537, Canela, RS, Brazil, July 1995.
[12] MIDORIKAWA, E. T. Uma nova estratégia para a gerência de memória para sistemas de computação de alto desempenho. Ph.D. Thesis. University of São Paulo, São Paulo, Brazil 1997.
[13] MIDORIKAWA, E. T. Otimização de localidade de dados em aplicações reais e estratégias de alocação dinâmica de memória. In: Proceedings of 10th Brazilian Symposium on Computer Architecture - High Performance Computing, Búzios, RJ, Brazil, October, 1998.
[14] C. D. Polychronopoulos. Parallel programming and compilers. Kluwer Academic Publishers, 1988.
[15] S. Takahashi et alii. Análise do padrão de acessos e otimização de localidade em sistemas de computação de alto desempenho. In: Proceedings of PANEL’95 (CTIC’95), v.2, p.1479, Canela, RS, Brazil, July 1995.
[16] TANENBAUM, A. S. & WOODHULL, A. S. Operating systems: design and implementation. 2nd. Ed., Prentice-Hall , 1997.
[17] VEENSTRA, J. E. & FOWLER, R. J. MINT tutorial and user manual. Technical report 452, Computer Science Department, University of Rochester, 1994.
[18] WOLFE, M. High performance compilers for parallel computing. Addison-Wesley, 1996.
[2] BANERJEE, U. Loop parallelization. Kluwer Academic Publishers, 1994.
[3] COCKCROFT, A. Sun performance and tuning: sparc & solaris. Prentice-Hall, 1995.
[4] EISENBEIS, C. et alii. A strategy for array management in local memory. Rapports de Recherche no 1262. INRIA, France. 1990.
[5] FRANKLIN, M. A. et alii. Anomalies with variable partition paging algorithms. Communications of the ACM, 21:3, p.232-236, 1978.
[6] K. Hwang. Advanced computer architecture: parallelism, scalability, programmability. McGraw-Hill, 1993.
[7] KREMER, U. Automatic data layout for distributed memory machines. Ph.D. Thesis. Computer Science Department, Rice University. 1995.
[8] MALKAWI, M. I. Compiler directed memory management for numerical programs. Ph.D. Thesis. Department of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign. 1986.
[9] MARINO, M. D. Pulsar: um sistema de memória virtual compartilhada e distribuída, baseado em consistência relaxada. Master Thesis, Polytechnic School, University of São Paulo, 1996.
[10] MIDORIKAWA, E. T. Análise da otimização de acessos à memória. In: Proceedings of 6th Brazilian Symposium on Computer Architecture - High Performance Computing, p.37-52, Caxambu, MG, Brazil, August 1994.
[11] MIDORIKAWA, E. T. et alii. Um sistema integrado para otimização automática de paralelismo e localidade de dados. In: Proceedings of 7th Brazilian Symposium on Computer Architecture - High Performance Computing, p.523-537, Canela, RS, Brazil, July 1995.
[12] MIDORIKAWA, E. T. Uma nova estratégia para a gerência de memória para sistemas de computação de alto desempenho. Ph.D. Thesis. University of São Paulo, São Paulo, Brazil 1997.
[13] MIDORIKAWA, E. T. Otimização de localidade de dados em aplicações reais e estratégias de alocação dinâmica de memória. In: Proceedings of 10th Brazilian Symposium on Computer Architecture - High Performance Computing, Búzios, RJ, Brazil, October, 1998.
[14] C. D. Polychronopoulos. Parallel programming and compilers. Kluwer Academic Publishers, 1988.
[15] S. Takahashi et alii. Análise do padrão de acessos e otimização de localidade em sistemas de computação de alto desempenho. In: Proceedings of PANEL’95 (CTIC’95), v.2, p.1479, Canela, RS, Brazil, July 1995.
[16] TANENBAUM, A. S. & WOODHULL, A. S. Operating systems: design and implementation. 2nd. Ed., Prentice-Hall , 1997.
[17] VEENSTRA, J. E. & FOWLER, R. J. MINT tutorial and user manual. Technical report 452, Computer Science Department, University of Rochester, 1994.
[18] WOLFE, M. High performance compilers for parallel computing. Addison-Wesley, 1996.
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Published
1999-03-01
How to Cite
Toshimi Midorikawa, E., Matsumoto Sato, L., & Zuffo, J. A. (1999). Communion: a new strategy form memory management in high-performance computer. Journal of Computer Science and Technology, 1(01), 16 p. Retrieved from https://journal.info.unlp.edu.ar/JCST/article/view/1025
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