Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling.

  • Adrian Pousa III-LIDI (Institute of Research in Computer Sciences LIDI), Facultad de Informática. Universidad Nacional de La Plata. La Plata, 1900, Argentina.

Abstract

Most of chip multiprocessors (CMPs) are symmetric, i.e. they are composed of identical cores. These CMPs may consist of complex cores (e.g., Intel Haswell or IBM Power8) or simple and lower-power cores (e.g. ARM Cortex A9 or Intel Xeon Phi). Cores in the former approach have advanced microarchitectural features, such as out-of-order super-scalar pipelines, and they are suitable for running sequential applications which use them efficiently. Cores in the latter approach have a simple microarchitecture and are good for running applications with high thread-level parallelism (TLP).

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References

[1] Rakesh Kumar y col. “Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload PerformaMichela Becchi y Patrick Crowley. \Dynamic Thread Assignment on Heterogeneous
[2] Michela Becchi y Patrick Crowley. “Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures”. Proc. of CF 06 (2006), pags. 29-40.
[3] N. Chitlur y col. “QuickIA: Exploring heterogeneous architectures on real prototypes”. HPCA 12 (2012), pags. 1-8.
[4] Matt Gillespie. “Preparing for The Second Stage of Multi-Core HW: Asymmetric (Heterogeneous) Cores”. Intel White Paper (2008).
[5] David Koufaty, Dheeraj Reddy y Scott Hahn. “Bias Scheduling in Heterogeneous Multi-core Architectures”. Proc. of Eurosys 10 (2010).
[6] Daniel Shelepov y col. “HASS a Scheduler for Heterogeneous Multicore Systems”. ACM SIGOPS OSR 43.2 (2009).
Published
2018-06-07
How to Cite
Pousa, A. (2018). Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling. Journal of Computer Science and Technology, 18(01), e09. https://doi.org/10.24215/16666038.18.e09
Section
Thesis Overview